Description of the Related Technology
The disclosed technology relates to semiconductor technology, and particularly to a FinFET with a gate stack intersecting two fins on an isolation layer, and methods for manufacturing the same.
Description of the Related Technology
Short channel effects are getting more significant as planar semiconductor devices are increasingly scaled down. To this end, three-dimensional (3D) semiconductor devices, such as fin field effect transistors (FinFETs), have been proposed. Generally, a FinFET includes a fin formed vertically on a substrate and a gate stack intersecting the fin. As such, a channel is formed in the fin, and has a width defined basically by a height of the fin. Unfortunately, it is difficult to control fins formed on a wafer to have the same height during manufacture of an integrated circuit (IC), resulting in inconsistency in performance of devices across the wafer.
On the other hand, a parasitic capacitance is formed at the bottom of the fin due to dielectric between the gate and the fin. If the parasitic capacitance is too large, the response time of the device will become too long.